1. Field of the Invention
This invention relates semiconductor devices so designed and arranged as to facilitate the testing of same. While not so limited the invention is primarily concerned with large scale integrated (LSI) chip or semiconductor devices having memory arrays and similar devices embedded therein, the array incorporating address, data and buffer registers.
For purposes of discussion the term "embedded" is defined as that condition of a memory array, circuit element or even a circuit function on an LSI chip, when surrounded by other circuitry on the chip, such that the memory array, circuit element or circuit function is not directly accessible, either in whole or in part, from the input and output terminals or pads of the chip.
A prime problem associated with such devices is the testing of the embedded array and, in particular, in getting the proper test data and address words to the array inputs. When there is a substantial amount of logic surrounding the array the problem is determining what input pattern or sequence of input patterns, if any, can be applied to the primary inputs of the device in order to get the correct pattern at the array, and, thereafter, to obtain meaningful test data results from the device output.
With the advent of large scale integration, the circuit designer as well as the component manufacturer are provided with the ability to increase greatly the number of circuits on a single chip of semiconductor material. But unless some means is provided for permitting testing of circuitry embedded within the chip, further increases in circuit density can not be expected.
2. Description of the Prior Art
Of course, the problem of testing LSI chips has been addressed before. One example, is the level sensitive testing technique of E. B. Eichelberger, U.S. Pat. No. 3,761,695 issued Sept. 25, 1973, and assigned to the same assignee as the present invention. M. T. McMahon, Jr., U.S. Pat. No. 3,781,670 issued Dec. 25, 1973, and assigned to the same assignee as the present invention allows a.c. performance testing of an LSI chip during fabrication. R. L. James, U.S. Pat. No. 3,789,205 issued Jan. 29, 1974, and assigned to the same assignee as the present invention, teaches testing individual chips mounted on a planar board while the chips are interconnected so as to perform a desired logical function by electronically isolating the chips and applying test patterns to the input lines of the chips to be tested. R. L. James, U.S. Pat. 3,790,885 issued Feb. 5, 1974, and assigned to the same assignee as the present invention, describes a method of testing LSI chips which comprises adding to the chip device, shift register storage means, loading a test pattern into the shift register storage means, applying the test pattern to selected elements of the chip device and monitoring the results.
Still other techniques addressing the problem of testing LSI chips are disclosed in: T. H. Baker, et al., U.S. Pat. No. 3,762,027 issued Oct. 2, 1973, and assigned to the same assignee as the present invention; and, DeWolf, U.S. Pat. No. 3,772,595, issued Nov. 13, 1973.
None of the above, however, provide a solution for the testing of embedded arrays.